The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Jun. 12, 2014
Applicant:

Tdk Corporation, Tokyo, JP;

Inventors:

Hiroyuki Uematsu, Tokyo, JP;

Kenichi Kawabata, Tokyo, JP;

Assignee:

TDK CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/42 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/115 (2013.01); H05K 1/185 (2013.01); H05K 3/427 (2013.01); H05K 1/188 (2013.01); H05K 3/0035 (2013.01); H05K 3/0038 (2013.01); H05K 2201/0187 (2013.01); H05K 2201/09563 (2013.01); H05K 2203/095 (2013.01); Y10T 29/4913 (2015.01); Y10T 29/49146 (2015.01); Y10T 29/49147 (2015.01); Y10T 29/49165 (2015.01);
Abstract

A wiring board or an electronic component embedded substrate includes a substrate that includes a resin containing a plurality of fillers; and a via that is electrically connected to at least one interconnect provided to the substrate, wherein the via includes a mix area in which metal is provided between the fillers on an inner radial side with respect to the substrate. A method of manufacturing a wiring board or an electronic component embedded substrate includes preparing a substrate that includes a resin containing a plurality of fillers; forming a via formation hole in the substrate; performing an ashing process on at least an inner wall of the via formation hole; and performing electroless plating on the inner wall of the via formation hole.


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