The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Oct. 05, 2012
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Krishna Kishor Noru, San Jose, CA (US);

Nitin Jadon, Burhanpur, IN;

Shu-Jen Fang, Miaoli County, TW;

Prahlad Venkatapuram, San Jose, CA (US);

Visalakshi Vaduganathan, Fremont, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 7/68 (2006.01); H04N 19/895 (2014.01); H04N 19/139 (2014.01); H04N 19/176 (2014.01); H04N 19/102 (2014.01); H04N 19/16 (2014.01);
U.S. Cl.
CPC ...
H04N 19/895 (2014.11); H04N 19/102 (2014.11); H04N 19/139 (2014.11); H04N 19/16 (2014.11); H04N 19/176 (2014.11);
Abstract

Techniques for synchronizing error concealment during video decoding include determining a decoding error. A recovery point within a current frame is determined for each decoding error. The determined recovery point may be the start of the next good slice of a frame after the current frame containing the error. The number of macroblock to be concealed is also determined. The determined number of macroblocks from the recovery point may then be concealed in hardware or software. The techniques for concealing errors may also include determining available macroblocks for use in concealing the error. The techniques for concealing errors may further include selecting a given concealment mode.


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