The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Jan. 18, 2013
Applicant:

Lsi Corporation, San Jose, CA (US);

Inventors:

Peter Kiss, Basking Ridge, NJ (US);

Said E. Abdelli, Minneapolis, MN (US);

Donald R. Laturell, Oak Hill, FL (US);

James F. MacDonald, Mendota Heights, MN (US);

Ross S. Wilson, Menlo Park, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/03 (2006.01); H04L 1/00 (2006.01); G06F 17/10 (2006.01); H03M 13/23 (2006.01); H03M 7/30 (2006.01); H03M 13/41 (2006.01);
U.S. Cl.
CPC ...
H04L 1/0059 (2013.01); G06F 17/10 (2013.01); H03M 7/3022 (2013.01); H03M 13/23 (2013.01); H03M 13/41 (2013.01);
Abstract

A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input signal.


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