The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2016
Filed:
Apr. 17, 2014
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Thomas Kuenemund, Munich, DE;
Bernhard Lippmann, Landshut, DE;
Assignee:
INFINEON TECHNOLOGIES AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/21 (2006.01); H01L 27/02 (2006.01); H01L 27/118 (2006.01); H03K 19/177 (2006.01); H01L 23/00 (2006.01); H01L 21/70 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H03K 19/215 (2013.01); H01L 23/576 (2013.01); H01L 27/0203 (2013.01); H01L 27/0207 (2013.01); H01L 27/11807 (2013.01); H03K 19/17768 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01);
Abstract
According to one embodiment, a chip is described comprising a plurality of supply lines delimiting a plurality of cell areas and a gate comprising a first transistor and a second transistor, wherein the first transistor is located in a first cell area of the plurality of cell areas and the second transistor is located in a second cell area of the plurality of cell areas such that a supply line of the plurality of supply lines lies between the first cell area and the second cell area.