The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

May. 29, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Le Wang, San Diego, CA (US);

Arash Mehrabi, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/26 (2006.01); H03B 5/04 (2006.01); H03B 5/20 (2006.01); H04B 5/04 (2006.01); H03K 3/30 (2006.01); H03K 3/0231 (2006.01); H03K 4/50 (2006.01);
U.S. Cl.
CPC ...
H03B 5/04 (2013.01); H03B 5/20 (2013.01); H03K 3/0231 (2013.01); H03K 3/30 (2013.01); H03K 4/50 (2013.01); H04B 5/04 (2013.01);
Abstract

Cancelling a delay in a comparator of an RC oscillator configured to generate a clock pulse, including: selectively coupling a plurality of current sources to a first capacitor, a second capacitor, and a resistor, wherein the plurality of current source charge and discharge the first capacitor and the second capacitor, and charge the resistor; charging the first capacitor at a higher rate during a first phase of the clock pulse than a second phase of the clock pulse, and charging the second capacitor at a higher rate during a third phase of the clock pulse than a fourth phase of the clock pulse; and generating the clock pulse by enabling the comparator to compare a voltage on the first or second capacitor with a voltage on the resistor.


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