The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2016
Filed:
Sep. 17, 2015
Hitachi, Ltd., Chiyoda-ku, Tokyo, JP;
Yoshitaka Sasago, Tachikawa, JP;
Akio Shima, Hino, JP;
Satoru Hanzawa, Hachioji, JP;
Takashi Kobayashi, Higashimurayama, JP;
Masaharu Kinoshita, Tsukuba, JP;
Norikatsu Takaura, Tokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line () which is provided above the substrate; a first laminated body, which is disposed above the first word line (), and which has the N+1 (N≧1) number of first inter-gate insulating layers (-) and the N number of first semiconductor layers (-) alternately laminated in the height direction of the substrate; a first bit line (), which extends in the direction that intersects the first word line (), and which is disposed above the laminated body; a first gate insulating layer () which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (-) and those of the N number of the first semiconductor layers (-); a first channel layer () which is provided on the side surface of the first gate insulating layer (); and a first variable resistance material layer () which is provided on the side surface of the first channel layer. The first variable material layer () is in a region where the first word line () and the first bit line () intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.