The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Feb. 03, 2015
Applicant:

Nxp B.v., Eindhoven, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/201 (2006.01); H01L 29/205 (2006.01); H01L 23/31 (2006.01); H01L 29/872 (2006.01); H01L 29/267 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 23/3171 (2013.01); H01L 29/201 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/267 (2013.01); H01L 29/405 (2013.01); H01L 29/872 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A heterojunction semiconductor device () comprising a substrate () and a multilayer structure disposed on the substrate. The multilayer structure comprising a first layer (), which comprises a first semiconductor disposed on top of the substrate, and a second layer (), which comprises a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas () forms adjacent to the interface. The multilayer structure also comprising a passivation layer, which comprises a semiconductor passivation layer () disposed on top of the second layer. The heterojunction semiconductor device also includes a first terminal () electrically coupled to a first area of the heterojunction semiconductor device; and a second terminal () electrically coupled to a second area of the heterojunction semiconductor device. The second terminal () is electrically coupled to the semiconductor passivation layer such that electric charge can flow into the second terminal () from the semiconductor passivation layer ().


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