The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Aug. 09, 2013
Applicant:

Shenzhen Sunmoon Microelectronics Co., Ltd., Shezhen, Guangdong, CN;

Inventor:

Zhaohua Li, Shenzhen, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 1/36 (2007.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/808 (2006.01); H01L 27/085 (2006.01); H03K 17/22 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0623 (2013.01); H01L 27/085 (2013.01); H01L 29/7817 (2013.01); H01L 29/7832 (2013.01); H01L 29/7835 (2013.01); H01L 29/808 (2013.01); H02M 1/36 (2013.01); H01L 27/0203 (2013.01); H03K 17/22 (2013.01);
Abstract

A high voltage device with composite structure comprises a high voltage power MOS transistor HVNMOS and a JFET. The high voltage power MOS transistor HVNMOS comprises a drain, a source, a gate and a substrate, and a P-type well region Pwell as a conducting channel which is arranged between the source and the drain. The JFET comprises the drain, the source, the gate and the substrate, and an N-type well region Nwell as a conducting channel which is arranged between the source and the drain. The high voltage power MOS transistor HVNMOS and the JFET share the same drain, and the drain is processed by using N-type double diffusion process. The embodiment of the present invention further presents a starting circuit using the high voltage device with composite structure.


Find Patent Forward Citations

Loading…