The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9385124 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 05, 2016

Filed:

Sep. 04, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Wen Pin Peng, Clifton Park, NY (US);

Min-hwa Chi, Malta, NY (US);

Garo Jacques Derderian, Saratoga Springs, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/311 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 29/165 (2013.01); H01L 29/6653 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01);
Abstract

One method disclosed herein includes, among other things, forming a first spacer proximate gate structures of first and second transistors that are opposite type transistors, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, performing a timed, wet etching process on both of the transistors so as to completely remove the layer of second spacer material from the second transistor while leaving a reduced thickness second spacer positioned adjacent the first spacer of the first transistor, wherein the reduced thickness second spacer has a thickness that is less than an initial thickness of the initial second spacer, and forming a third spacer on and in contact with the first spacer of the second transistor.


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