The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Nov. 03, 2014
Applicants:

Sangwon Kim, Hwasung, KR;

Seunghun Han, Hwasung, KR;

Inventors:

Sangwon Kim, Hwasung, KR;

Seunghun Han, Hwasung, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 25/10 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 23/3128 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1082 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18161 (2013.01);
Abstract

Provided are semiconductor packages and methods of fabricating the same. In one embodiment, the package may include an upper package stacked on a lower package, and a plurality of connection terminals electrically connecting the lower and upper packages. The lower package may include a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, and a lower mold layer provided on the lower package substrate to mold the lower semiconductor chip. The lower mold layer may have a trench-shaped first opening through which the lower package substrate is exposed in a substantially line shape. The connection terminals may be electrically connected to the lower package substrate exposed by the first opening and be not in contact with the lower mold layer.


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