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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9385057 B1

PDFFull Text
Date of Patent:
Jul. 05, 2016

Filed:

Sep. 15, 2014

Semiconductor device

Applicant:

Seiko Instruments Inc., Chiba-shi, Chiba, JP;

Inventor:

Tomoyuki Yoshino, Chiba, JP;

Assignee:

SII Semiconductor Corporation, , JP;

Attorney:

Adams & Wilks

Primary Examiner:

Phuc Dang

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/28 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/28 (2013.01); H01L 21/4821 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/78 (2013.01); H01L 23/49541 (2013.01); H01L 23/49582 (2013.01); H01L 23/49861 (2013.01); H01L 24/97 (2013.01); H01L 24/73 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/45139 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/97 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor flat package has a semiconductor chip, leads connected to the semiconductor chip, and an encapsulation resin covering the semiconductor chip and partially covering the leads. Outer end surfaces of the leads are exposed from the encapsulation resin and covered with a plated layer, and a side end surface of the plated layer and a side end surface of the encapsulation resin are flush with each other. A material with good solder wettability is formed at a lead cut portion of the semiconductor flat package, to thereby improve solder connection strength with a circuit board. A solder fillet is formed from the lead cut portion of the semiconductor package, to thereby enable adaptation of solder automatic visual inspection after mounting.

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