The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Mar. 10, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Theodoros A. Antonakopoulos, Patras, GR;

Evangelos Eleftheriou, Rüschlikon, CH;

Ioannis Koltsidas, Zurich, CH;

Peter Mueller, Zurich, CH;

Aspasia Palli, Eleusis, GR;

Roman A. Pletka, Uster, CH;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 14/00 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0045 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 13/003 (2013.01); G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0023 (2013.01); G11C 13/0061 (2013.01); G11C 13/0069 (2013.01); G11C 7/10 (2013.01); G11C 2013/0088 (2013.01);
Abstract

A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.


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