The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Aug. 27, 2008
Applicants:

Maxim Adelman, New York, NY (US);

Jon C. R. Bennett, Sudbury, MA (US);

Inventors:

Maxim Adelman, New York, NY (US);

Jon C. R. Bennett, Sudbury, MA (US);

Assignee:

VIOLIN MEMORY, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G11C 11/4076 (2006.01); G06F 1/32 (2006.01); G11C 5/04 (2006.01); G11C 11/406 (2006.01); G11C 11/4074 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G06F 1/3203 (2013.01); G06F 1/3225 (2013.01); G06F 1/3275 (2013.01); G06F 3/064 (2013.01); G06F 3/0688 (2013.01); G11C 5/04 (2013.01); G11C 11/406 (2013.01); G11C 11/4074 (2013.01); G11C 11/40611 (2013.01); G11C 2211/4067 (2013.01); Y02B 60/1225 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/32 (2013.01);
Abstract

A memory system is described, where a plurality of memory modules is connected to a memory controller. The power status of each of the memory modules is controlled, depending on the functions being performed by the memory module. When no read or write operation is being performed on a particular memory module, at least a portion of the circuitry may be operated in a lower power mode. A memory circuit associated with the memory module may be placed in a low power mode by disabling a clock. The memory circuit data integrity may be secured by issuing refresh commands while when the memory circuit is in the lower power mode, by enabling the clock, issuing the refresh command, and disabling the clock after completion of the refresh operation.


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