The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Dec. 23, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY (US);

Inventors:

Anthony R. Bonaccio, Shelburne, VT (US);

John K. DeBrosse, Colchester, VT (US);

Thomas M. Maffitt, Burlington, VT (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/02 (2006.01); G11C 7/06 (2006.01); G11C 11/16 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G11C 7/065 (2013.01); G11C 7/062 (2013.01); G11C 11/1673 (2013.01); G11C 29/026 (2013.01); G11C 29/028 (2013.01);
Abstract

Embodiments are directed to a self-reference STT-MRAM sensing scheme that uses offset-cancellation to reduce the impact of FET mismatch and thereby allow the sensing of lower read voltages. In some embodiments, the sensing scheme includes a differential amplifier having a first input connected to a memory cell. In some embodiments, a second input of the differential amplifier may be connected to ground, a common mode voltage of the system or a mid-level supply voltage. The present disclosure provides flexibility with respect to the voltage level at which the sensing is performed (e.g., ground, Voc, Vmid, etc.). The present disclosure provides further flexibility with respect to the sense voltage polarity.


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