The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Nov. 21, 2013
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Nhon Quach, San Jose, CA (US);

Stephen Z. Au, Union City, CA (US);

Thomas Zou, Millbrae, CA (US);

Tracy Sharpe, Seattle, WA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/24 (2006.01); G06F 13/28 (2006.01); G06F 13/32 (2006.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/32 (2013.01); G06F 13/24 (2013.01); G06F 13/28 (2013.01); G06F 13/385 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/0038 (2013.01);
Abstract

One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA® bus. The interconnect chip may communicate with the IO device via the AMBA® bus in an AMBA® compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA® bus, receiving a response from the IO device over the AMBA® bus, and sending over the AMBA® bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.


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