The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Nov. 27, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Daniel M Crowell, Rochester, MN (US);

James S Fields, Austin, TX (US);

Richard B Finch, New Paitz, NY (US);

Harald Pross, Wildberg, DE;

Gerald G Stanquist, Salt Point, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/319 (2006.01); G11C 29/56 (2006.01); G06F 11/22 (2006.01); G06F 11/273 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2236 (2013.01); G06F 11/273 (2013.01);
Abstract

A testing backplane apparatus includes first test ports configured to receive a first processor assembly under test and the plurality of first test ports may be an even number of first test ports or an odd number of first test ports. The testing backplane apparatus includes second test ports, where each first test port corresponds to a second test port and the second test ports connect to a second processor assembly. The testing backplane apparatus includes a signal pathway from each first test port to a second test port. The signal pathway includes a signal path length within a range between a maximum signal path length and a minimum signal path length. Each port on the first processor assembly corresponds to each port on the second processor assembly and the testing backplane apparatus is configured differently from a backplane used as a final destination for operating the first processor assembly.


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