The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

May. 31, 2013
Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Hideyuki Yamamoto, Tokyo, JP;

Xianchun Xu, Tokyo, JP;

Toru Takahashi, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/46 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5077 (2013.01);
Abstract

An apparatus predicts time-series variations in resource usage for logical structures for a future time period (a schedule period) on the basis of a history representing the history of resource usage by the logical structures. The apparatus attempts to select a plurality of arrangement candidates for which resource usage in each of a plurality of physical machines is equal to or less than a criterion for each of a plurality of time segments comprising the schedule period. The apparatus computes a migration cost of migrating the logical structures between physical machines for an arrangement according to a holistic arrangement plan for each of a plurality of holistic arrangement plans. Each of the plurality of holistic arrangement plans is a combination of a plurality of selected arrangement candidates corresponding to each of the plurality of time segments.


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