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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9384016 B1

PDFFull Text
Date of Patent:
Jul. 05, 2016

Filed:

Mar. 14, 2014

Method of estimating program speed-up with highly parallel architectures

Applicant:

Wisconsin Alumni Research Foundation, Madison, WI (US);

Inventors:

Karthikeyan Sankaralingam, Madison, WI (US);

Newsha Ardalani, Madison, WI (US);

Xiaojin Zhu, Middleton, WI (US);

Assignee:

Wisconsin Alumni Research Foundation, Madison, WI (US);

Attorney:

Boyle Fredrickson, S.C.

Primary Examiner:

Lechi Truong

Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 19/00 (2011.01); G06F 9/445 (2006.01); G06F 9/54 (2006.01); G05B 23/02 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
G06F 9/44505 (2013.01); G05B 23/0294 (2013.01); G06F 8/443 (2013.01); G06F 9/54 (2013.01);
Abstract

The amount of speed-up that can be obtained by moving a program to a parallel architecture is determined by a model associating speed-up to micro-architecture independent features of the program execution. The model may be generated, for example, by linear regression, by evaluating programs that have been ported to parallel architectures where the micro-architecture independent features are known.

Find Patent Forward Citations

Sankaralingam, Karthikeyan. (2016). Method of estimating program speed-up with highly parallel architectures (U.S. Patent No. 9384016). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9384016

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