The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Aug. 15, 2012
Applicants:

Ben Hertzberg, Santa Clara, CA (US);

Nathan Tuck, Corvallis, OR (US);

Inventors:

Ben Hertzberg, Santa Clara, CA (US);

Nathan Tuck, Corvallis, OR (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2006.01); G06F 9/30 (2006.01); G06F 9/40 (2006.01); G06F 9/32 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30174 (2013.01); G06F 9/322 (2013.01); G06F 9/3808 (2013.01);
Abstract

A processing system includes a microprocessor, a hardware decoder arranged within the microprocessor, and a translator operatively coupled to the microprocessor. The hardware decoder is configured to decode instruction code non-native to the microprocessor for execution in the microprocessor. The translator is configured to form a translation of the instruction code in an instruction set native to the microprocessor and to connect a branch instruction in the translation to a chaining stub. The chaining stub is configured to selectively cause additional instruction code at a target address of the branch instruction to be received in the hardware decoder without causing the processing system to search for a translation of additional instruction code at the target address.


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