The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2016
Filed:
Nov. 13, 2013
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Dexter Chun, San Diego, CA (US);
Haw-Jing Lo, San Diego, CA (US);
Assignee:
QUALCOMM INCORPORATED, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/32 (2006.01); G11C 7/10 (2006.01); G11C 11/4096 (2006.01); G06F 7/76 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3275 (2013.01); G11C 7/1009 (2013.01); G06F 1/32 (2013.01); G06F 1/3253 (2013.01); G06F 7/764 (2013.01); G11C 7/1006 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 11/4096 (2013.01);
Abstract
Systems and methods are disclosed for reducing memory I/O power. One embodiment is a system comprising a system on chip (SoC), a DRAM memory device, and a data masking power reduction module. The SoC comprises a memory controller. The DRAM memory device is coupled to the memory controller via a plurality of DQ pins. The data masking power reduction module comprises logic configured to drive the DQ pins to a power saving state during a data masking operation.