The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Jul. 14, 2011
Applicants:

Brian Salsbery, Superior, CO (US);

Christopher Lee Medrano, Longmont, CO (US);

Inventors:

Brian Salsbery, Superior, CO (US);

Christopher Lee Medrano, Longmont, CO (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/04 (2006.01); G06F 1/32 (2006.01); G06F 1/20 (2006.01); G06F 1/08 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3237 (2013.01); G06F 1/203 (2013.01); G06F 1/324 (2013.01); G06F 1/3287 (2013.01); G06F 1/08 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/1221 (2013.01); Y02B 60/1282 (2013.01);
Abstract

A system and method for reducing heat in a portable computing device includes clocking a processor such that it is provided with a full frequency over time tto t. A timer is set to trigger a forced power collapse ('FPC') that removes all power to the processor from time tto time t. At time t, the processor may be awakened such that it can resume processing at the full frequency. Advantageously, during the FPC, no leakage power ('P') is consumed by the processor between tand t. The result is that the processor averages the same processing efficiency over time tto tas it otherwise would have if a reduced frequency had been provided to it. However, because no Pwas consumed during the FPC, the generation of heat between time tand tthat is related to Pis avoided.


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