The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2016

Filed:

Jun. 16, 2015
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Huai-Te Wang, Taoyuan, TW;

Tsung-Hsin Chou, Nantou County, TW;

Chih-Hsien Lin, Hsinchu County, TW;

Bo-Jiun Chen, New Taipei, TW;

Yan-Bin Luo, Taipei, TW;

Assignee:

MEDIATEK INC., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/40 (2006.01); H04L 25/03 (2006.01); H03L 7/091 (2006.01); H03L 7/095 (2006.01); H03L 7/087 (2006.01); H03L 7/099 (2006.01); H04L 7/033 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03057 (2013.01); H03L 7/087 (2013.01); H03L 7/091 (2013.01); H03L 7/095 (2013.01); H03L 7/099 (2013.01); H04L 7/0331 (2013.01); H04L 7/0025 (2013.01);
Abstract

A method for performing data sampling control in an electronic device and an associated apparatus are provided, where the method includes the steps of: detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; and when the data sampling time shift configuration is triggered, utilizing a phase shift clock, rather than a normal clock corresponding to a normal configuration of the DFE receiver, as an edge sampler clock of an edge sampler in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver.


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