Process for fabricating a field-effect transistor device implemented on a network of vertical nanowires, the resulting transistor device, an electronic device comprising such transistor devices and a processor comprising at least one such device

Abstract

A process for fabricating a field-effect transistor device () implemented on a network of vertical nanowires (), includes: producing a source electrode () and a drain electrode () at each end of each nanowire () symmetrically relative to the gate electrode of each elementary transistor implemented on a nanowire; creating a gate electrode by depositing a layer () of conductive material around a layer () of dielectric material that surrounds a portion of each nanowire (), a single conductive layer () being used for all of the nanowires and the thickness of the conductive layer corresponding to the gate length of the transistor device; and insulating each electrode with a planar layer () of a dielectric material in order to form a nanoscale gate and in order to insulate the contacts of each elementary transistor between the gate and the source and the gate and the drain.