The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2016
Filed:
Nov. 28, 2015
Applicant:
Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;
Inventors:
Kazuo Sakamoto, Tokyo, JP;
Naozumi Morino, Tokyo, JP;
Kazuo Tanaka, Tokyo, JP;
Hiroyasu Ishizuka, Tokyo, JP;
Assignee:
Renesas Electronics Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01); H01L 27/02 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0288 (2013.01); H01L 27/11898 (2013.01);
Abstract
A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.