The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2016

Filed:

May. 14, 2015
Applicants:

Jungwoo Kim, Osan-si, KR;

Jingyu Kim, Asan-si, KR;

Inventors:

Jungwoo Kim, Osan-si, KR;

Jingyu Kim, Asan-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 25/00 (2006.01); H01L 23/31 (2006.01); H05K 7/02 (2006.01); H01L 25/16 (2006.01); H01L 21/52 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/565 (2013.01); H01L 21/52 (2013.01); H01L 21/56 (2013.01); H01L 23/3107 (2013.01); H01L 23/3128 (2013.01); H01L 25/105 (2013.01); H01L 25/162 (2013.01); H01L 25/50 (2013.01); H05K 7/023 (2013.01); H01L 24/11 (2013.01); H01L 24/81 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/18161 (2013.01);
Abstract

A semiconductor package includes a lower package comprising a lower semiconductor chip mounted on a lower package substrate, an upper package comprising an upper package substrate stacked on the lower package and an upper semiconductor chip mounted on the upper package substrate, interconnection terminals electrically connecting the lower package substrate with the upper package substrate, and a lower molding film molding the lower semiconductor chip between the lower package substrate and the upper package substrate. The lower package substrate comprises a chip region on which the lower semiconductor chip is mounted, an interconnection region enclosing a portion of the chip region, and a mold injection region defined by the chip region and the interconnection region. The interconnection terminals are disposed on the lower package substrate of the interconnection region but not disposed on the lower package substrate of the mold injection region.


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