The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2016
Filed:
Jun. 07, 2012
Stanton Petree Ashburn, McKinney, TX (US);
Daniel L. Corum, Richardson, TX (US);
Abha Singh Kasper, Fairview, TX (US);
Harold C. Waite, Rockwall, TX (US);
Eric D. Rullan, Allen, TX (US);
Donald L. Plumton, Dallas, TX (US);
Douglas A. Prinslow, McKinney, TX (US);
Stanton Petree Ashburn, McKinney, TX (US);
Daniel L. Corum, Richardson, TX (US);
Abha Singh Kasper, Fairview, TX (US);
Harold C. Waite, Rockwall, TX (US);
Eric D. Rullan, Allen, TX (US);
Donald L. Plumton, Dallas, TX (US);
Douglas A. Prinslow, McKinney, TX (US);
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Abstract
Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.