Resistive memory device capable of increasing sensing margin by controlling interface states of cell transistors

Abstract

A resistive memory device includes a memory cell array having a plurality of memory cells therein, which operate in response to word line driving and column selecting signals. Each of memory cells includes a resistive device and a cell transistor connected in series. An I/O sense amplifier senses and amplifies data output from the memory cell array to thereby generate output data, and also generate program current based on input data and provide the program current to the memory cell array. The resistive memory device is also configured to read output data from the I/O sense amplifier and adjust interface states of the cell transistors based on a voltage level of the output data during a test mode.