The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2016

Filed:

Aug. 06, 2014
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Sagheer Ahmad, Cupertino, CA (US);

Bradley L. Taylor, Santa Cruz, CA (US);

Giulio Corradi, Munich, DE;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G06F 11/20 (2006.01); H03K 19/177 (2006.01); H03K 19/007 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2007 (2013.01); H03K 19/007 (2013.01); H03K 19/17764 (2013.01);
Abstract

A system on a chip (SoC) for providing safety hardware fault tolerance and/or safety software fault tolerance includes a first safety sub-system having a first safety channel; a second safety sub-system having a second safety channel; and a third sub-system. The first safety sub-system is independent of the second safety sub-system to allow the second safety sub-system to communicate through the second safety channel when the first safety sub-system or the third subsystem fails, and further to allow the first safety sub-system to communicate through the first safety channel when the second safety sub-system or the third subsystem fails.


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