The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2016
Filed:
Jun. 28, 2012
Philip G. Emma, Danbury, CT (US);
Eren Kursun, Ossining, NY (US);
Jude A. Rivers, Cortlandt Manor, NY (US);
Philip G. Emma, Danbury, CT (US);
Eren Kursun, Ossining, NY (US);
Jude A. Rivers, Cortlandt Manor, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
A method for generating and implementing a three-dimensional (3D) computer processing chip stack plan that includes receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to a layer in the 3D computer processing chip stack plan. The method also includes identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The method further includes determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment generates and integrates both the layer including the common structures and technologies and the host layer including the uncommon structures and technologies to form the 3D computer processing chip stack.