The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2016

Filed:

May. 22, 2013
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Jean-Paul Garandet, Le Bourget du Lac, FR;

Etienne Pihan, La Motte Servolex, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); C30B 19/12 (2006.01); C30B 25/18 (2006.01); C30B 25/20 (2006.01); C30B 29/06 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02636 (2013.01); C30B 19/12 (2013.01); C30B 25/186 (2013.01); C30B 25/20 (2013.01); C30B 29/06 (2013.01); H01L 21/02439 (2013.01); H01L 21/02513 (2013.01); H01L 21/02532 (2013.01); H01L 21/02634 (2013.01); H01L 21/02639 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01);
Abstract

The present invention relates to a method for manufacturing an epitactic silicon layer made up of crystallites with a size no lower than 20 μm, including: providing a layer of crystallized silicon the surface of which, being inhomogeneous in terms of the size of the crystallites, is made up of large crystallites with a size no lower than 20 μm, and small crystallites of a smaller size; forming, on the surface of the inhomogeneous silicon layer, a layer of at least one non-nucleating material for the silicon, the thickness of which is adjusted such to cover the entire outer surface of the small crystallites, while leaving all or part of the outer surface of the large crystallites accessible; and carrying out epitaxial growth of a silicon layer on the surface of the assembly obtained at the end of step, under conditions that are suitable for forming the expected epitactic layer.


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