The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2016

Filed:

Jan. 02, 2014
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Russell Schreiber, Austin, TX (US);

Stephen Kosonocky, Fort Collins, CO (US);

Amlan Ghosh, Austin, TX (US);

Assignee:

ADVANCED MICRO DEVICES, INC., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/24 (2006.01); G11C 29/02 (2006.01); G11C 11/41 (2006.01); G11C 29/04 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 29/24 (2013.01); G11C 29/028 (2013.01); G11C 11/41 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/1204 (2013.01);
Abstract

A circuit with headroom monitoring includes a memory array having memory cells, a replica array, and a built-in self test circuit. The replica array has a plurality of word lines, a plurality of bit line pairs, and memory cells located at intersections of the plurality of word lines and the plurality of bit line pairs. The memory cells are of a same type as memory cells in the memory array. The built-in self test circuit is coupled to the replica array for adding a capacitance to at least one bit line of the plurality of bit line pairs, for sensing a read time of memory cells of the replica array with the capacitance so added, and for providing a headroom signal in response to the read time.


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