The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2016

Filed:

Jul. 28, 2009
Applicants:

David S. Christie, Austin, TX (US);

Michael P. Hohmuth, Dresden, DE;

Stephan Diestelhorst, Dresden, DE;

Inventors:

David S. Christie, Austin, TX (US);

Michael P. Hohmuth, Dresden, DE;

Stephan Diestelhorst, Dresden, DE;

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/52 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/466 (2013.01); G06F 9/3004 (2013.01); G06F 9/30087 (2013.01); G06F 9/30185 (2013.01); G06F 9/30189 (2013.01); G06F 9/3834 (2013.01); G06F 9/3842 (2013.01); G06F 9/3857 (2013.01); G06F 9/3863 (2013.01); G06F 9/468 (2013.01); G06F 9/52 (2013.01);
Abstract

A system and method for executing a transaction in a transactional memory system is disclosed. The system includes a processor of a plurality of processors coupled to shared memory, wherein the processor is configured to execute a section of code, including a plurality of memory access operations to the shared memory, as an atomic transaction relative to the execution of the plurality of processors. According to embodiments, the processor is configured to determine whether the memory access operations include any of a set of disallowed instructions, wherein the set includes one or more instructions that operate differently in a virtualized computing environment than in a native computing environment. If any of the memory access operations are ones of the disallowed instructions, then the processor aborts the transaction.


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