The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2016

Filed:

Jan. 21, 2014
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Sriram Sambamurthy, Austin, TX (US);

Arun Sundaresan Iyer, Bangalore, IN;

Alok Baluni, Bangalore, IN;

Aaron Grenat, Austin, TX (US);

Assignee:

Other;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03B 19/00 (2006.01); G06F 1/04 (2006.01); H03K 19/20 (2006.01); H03K 5/00 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/04 (2013.01); H03K 5/00006 (2013.01); H03K 19/0013 (2013.01); H03K 19/20 (2013.01);
Abstract

A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.


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