The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2016

Filed:

Jan. 11, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Song S Shi, San Diego, CA (US);

Pengfei Li, San Diego, CA (US);

Lennart Karl-Axel Mathe, San Diego, CA (US);

Yunfei Shi, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/156 (2006.01); G05F 3/02 (2006.01); H03F 1/02 (2006.01); H02M 3/155 (2006.01); H02M 3/158 (2006.01);
U.S. Cl.
CPC ...
G05F 3/02 (2013.01); H02M 3/155 (2013.01); H03F 1/0238 (2013.01); H02M 3/1582 (2013.01);
Abstract

Techniques for generating a boost clock signal for a boost converter from a buck converter clock signal, wherein the boost clock signal has a limited frequency range. In an aspect, the boost clock signal has a maximum frequency determined by Vbst/T, wherein Vbst represents the difference between a target output voltage and a battery voltage, and T represents a predetermined cycle duration. The boost converter may include a pulse insertion block to limit the minimum frequency of the boost clock signal, and a dynamic blanking/delay block to limit the maximum frequency of the boost clock signal. Further techniques are disclosed for generally implementing the minimum frequency limiting and maximum frequency limiting blocks.


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