The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2016
Filed:
Jun. 30, 2015
International Business Machines Corporation, Armonk, NY (US);
Matthew B. Baecher, Rock Tavern, NY (US);
John F. Bulzacchelli, Yonkers, NY (US);
John F. Ewen, Rochester, NY (US);
Gautam Gangasani, Hopewell Junction, NY (US);
Mounir Meghelli, I, Tarrytown, NY (US);
Matthew J. Paschal, Rochester, NY (US);
Trushil N. Shah, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Method and apparatus to calibrate sampling phases of a multi-phase sampling system. The method includes on-chip generating a pristine phase reference pattern signal for use in generating at least one reference output signal from a data path; sampling, responsive to a clock signal, the at least one reference output signal to obtain samples; and modifying a phase of the clock signal to align the obtained samples to pattern edges of at least one reference output signal. Both symmetric and asymmetric duty cycle distortion are removed from the pristine phase reference pattern signal input to the data path. The effects of asymmetric distortion in the data path output signal upon the phase calibration are cancelled by periodically inverting the at least one reference output signal. The method adjusts a first phase sampling clock signal output of an electronic phase rotator device to provide an initial alignment setting against a first edge of the reference output signal; and then implements phase calibration logic to align a second phase sampling clock signal against a second edge.