The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Nov. 15, 2013
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Daxiang Kang, Shanghai, CN;

Huaguo Xie, Shenzhen, CN;

Gaowei Luo, Shanghai, CN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04J 3/06 (2006.01); H04W 8/22 (2009.01); H04W 76/02 (2009.01); H04W 28/18 (2009.01); H04W 8/24 (2009.01); H04L 12/723 (2013.01);
U.S. Cl.
CPC ...
H04J 3/0667 (2013.01); H04W 8/22 (2013.01); H04W 76/02 (2013.01); H04L 45/50 (2013.01); H04W 8/245 (2013.01); H04W 28/18 (2013.01);
Abstract

Embodiments of the present invention provide a clock synchronization method and device. The method includes: receiving, a preconfigured multi-protocol label switching (MPLS) capability parameter and a traffic engineering (TE) capability parameter, and establishing, based on the MPLS capability parameter and the TE capability parameter, an MPLS tunnel interface; establishing, an MPLS TE tunnel whose bidirectional paths are consistent between the first clock synchronization device and a second clock synchronization device; and performing, clock synchronization message interaction with the second clock synchronization device through the established MPLS TE tunnel. In the embodiments of the present invention, by establishing the MPLS TE tunnel whose bidirectional paths are consistent between the first clock synchronization device and the second clock synchronization device which perform clock synchronization message interaction, symmetry of clock synchronization message interaction paths is ensured, and therefore, a time error in clock synchronization resulting from asymmetry of the paths is avoided.


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