Interconnect structures for minimizing clock and output timing skews in a high speed current steering dac

Abstract

A system includes a clock interconnect network having an input node and a plurality of output nodes. The clock interconnect network receives a clock input at the input node and distributes, based on the clock input, a plurality of clock signals via respective ones of the plurality of output nodes. A propagation delay of each of the plurality of clock signals distributed by the clock interconnect network is approximately equal to respective propagation delays of others of the plurality of clock signals distributed by the clock interconnect network. A digital-to-analog converter includes a plurality of segments, each outputting a respective output, and a plurality of drivers. Each of the plurality of drivers receives a respective one of the plurality of clock signals and provides a driver signal to a respective one of the plurality of segments based on the respective one of the plurality of clock signals.