The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2016
Filed:
Feb. 14, 2015
Integrated Device Technology, Inc., San Jose, CA (US);
Min Chu, Milpitas, CA (US);
Jagdeep Bal, Saratoga, CA (US);
INTEGRATED DEVICE TECHNOLOGY, inc., San Jose, CA (US);
Abstract
Methods and apparatuses are described to reduce phase noise in a low noise fractional reference-injection phase locked loop (FRIPLL). The FRIPLL includes a ring voltage controlled oscillator (VCO). An output of the ring VCO is input to a fractional interpolative frequency divider (FIFD). A signal comparison circuit receives a reference clock signal and a further delayed output of the FIFD. The signal comparison circuit produces a control voltage signal in response to a phase difference between the reference clock signal and the further delayed output of the FIFD. The control voltage signal is input to the ring VCO to control a ring VCO frequency. An oscillator control circuit has a first input and a second input. The first input is a first delayed output of the FIFD. The second input is the reference clock signal. The oscillator control circuit generates a realignment signal which is used to realign a state transition in a ring VCO output signal to the reference clock signal when the ring VCO output signal is in a low state. Realignment occurs repeatedly at a frequency of the reference clock signal.