The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Jul. 30, 2013
Applicant:

Alpha and Omega Semiconductor Incorporated, Sunnyvale, CA (US);

Inventor:

François Hébert, San Mateo, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2012.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 21/26586 (2013.01); H01L 29/0878 (2013.01); H01L 29/0886 (2013.01); H01L 29/66734 (2013.01);
Abstract

This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.


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