The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Mar. 29, 2013
Applicants:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Stmicroelectronics S.a., Montrouge, FR;

Inventors:

Philippe Galy, Le Touvet, FR;

Patrice Dehan, La Tronche, FR;

Boris Heitz, Grenoble, FR;

Jean Jimenez, Saint Théoffrey, FR;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 27/07 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78 (2013.01); H01L 27/0727 (2013.01); H01L 29/41775 (2013.01); H01L 29/66553 (2013.01); H01L 29/66628 (2013.01); H01L 29/66643 (2013.01); H01L 29/7839 (2013.01);
Abstract

An integrated circuit may include at least one MOS transistor having a sigmoid response. The at least one MOS transistor may include a substrate, a source region, a drain region, a gate region, and insulating spacer regions on either side of the gate region. The substrate may include a first region situated under the gate region between the insulating spacer regions. At least one of the source and drain regions may be separated from the first region of the substrate by a second region of the substrate situated under an insulating spacer region, which may be of a same type of conductivity as the first region of the substrate.


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