The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Jun. 25, 2015
Applicant:

Globalfoundaries Inc., Grand Cayman, KY (US);

Inventors:

Renata Camillo-Castillo, Essex Junction, VT (US);

Vibhor Jain, Essex Junction, VT (US);

Vikas K. Kaushal, Essex Junction, VT (US);

Marwan H. Khater, Astoria, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/732 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/737 (2006.01); H01L 21/764 (2006.01); H01L 21/265 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7371 (2013.01); H01L 21/26586 (2013.01); H01L 21/764 (2013.01); H01L 29/0649 (2013.01); H01L 29/0821 (2013.01); H01L 29/66242 (2013.01); H01L 29/66272 (2013.01); H01L 29/66287 (2013.01); H01L 29/732 (2013.01); H01L 29/0653 (2013.01);
Abstract

Fabrication methods for a device structure and device structures. A trench isolation region is formed that bounds an active device region of a semiconductor substrate. A first semiconductor layer is formed on the active device region and on the trench isolation region. A first airgap is formed between the first semiconductor layer and the active device region. A second airgap is formed between the first semiconductor layer and the trench isolation region. The first airgap extends into the active device region such that the height of the first airgap is greater than the height of the second airgap.


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