The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Mar. 17, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Kyungbum Koo, Yongin-si, KR;

Seungjae Lee, Hwaseong-si, KR;

Shinhye Kim, Suwon-si, KR;

Zulkamain, Yongin-si, KR;

Narae Oh, Bucheon-si, KR;

Jeong-Kyu Lee, Incheon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/283 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/31 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 27/11 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/283 (2013.01); H01L 21/31 (2013.01); H01L 21/31053 (2013.01); H01L 21/31055 (2013.01); H01L 21/31111 (2013.01); H01L 21/32133 (2013.01); H01L 21/768 (2013.01); H01L 23/528 (2013.01); H01L 27/1104 (2013.01); H01L 29/4232 (2013.01); H01L 29/78 (2013.01);
Abstract

Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The methods may include forming a sacrificial gate pattern on a substrate, forming a first spacer on a sidewall of the sacrificial gate pattern and forming a first interlayer dielectric (ILD) layer covering a sidewall of the first spacer and exposing a top surface of the first spacer. The first spacer may expose an upper portion of the sidewall of the sacrificial gate pattern. The methods may also include forming a capping insulating pattern covering top surfaces of the first spacer and the first ILD layer, replacing the sacrificial gate pattern with a gate electrode structure and patterning the capping insulating pattern to form a second spacer on the first spacer and between the gate electrode structure and the first ILD layer. The second spacer may be formed of a material having a dielectric constant higher than a dielectric constant of the first spacer.


Find Patent Forward Citations

Loading…