The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Jan. 09, 2015
Applicants:

Jung Geun Jee, Seoul, KR;

Dong Kyum Kim, Suwon-si, KR;

Jin Gyun Kim, Suwon-si, KR;

Ki Hyun Hwang, Seongnam-si, KR;

Inventors:

Jung Geun Jee, Seoul, KR;

Dong Kyum Kim, Suwon-si, KR;

Jin Gyun Kim, Suwon-si, KR;

Ki Hyun Hwang, Seongnam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/16 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11573 (2013.01); H01L 27/11521 (2013.01); H01L 27/11526 (2013.01); H01L 27/11568 (2013.01); H01L 29/16 (2013.01); H01L 29/788 (2013.01); H01L 29/792 (2013.01);
Abstract

There is provided a peripheral circuit region including a plurality of circuit elements disposed on a first substrate; and a cell region including at least one channel region extending from an upper surface of a second substrate disposed on the first substrate in a direction perpendicular to the upper surface of the second substrate, and a plurality of gate electrode layers and a plurality of insulating layers stacked on the second substrate to be adjacent to the at least one channel region, wherein at least a portion of the first substrate contacts the second substrate, and the first substrate and the second substrate provide a single substrate.


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