The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2016
Filed:
Oct. 29, 2014
Carolyn Rae Ellinger, Rochester, NY (US);
Shelby Forrester Nelson, Pittsford, NY (US);
Carolyn Rae Ellinger, Rochester, NY (US);
Shelby Forrester Nelson, Pittsford, NY (US);
EASTMAN KODAK COMPANY, Rochester, NY (US);
Abstract
An enhancement-mode inverter includes a load transistor and a drive transistor. The load transistor has a bottom gate architecture with a first source, a first drain, a load channel region, a first semiconductor layer, and a first gate electrode. A load gate dielectric is in the load channel region, and has a load dielectric thickness. The drive transistor has a bottom gate architecture with a second source, a second drain, a drive channel region, a second semiconductor layer, and a second gate electrode. A drive gate dielectric is in the drive channel region, and has a drive dielectric thickness less than the load dielectric thickness. The first source is electrically connected to the second drain and the first gate is electrically connected to the first drain. The load gate dielectric and the drive gate dielectric are part of a common shared dielectric stack.