The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2016

Filed:

Oct. 17, 2014
Applicant:

Spansion Llc, Sunnyvale, CA (US);

Inventor:

Calvin T. Gabriel, Cupertino, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76802 (2013.01); H01L 21/3065 (2013.01); H01L 21/31116 (2013.01); H01L 21/31138 (2013.01); H01L 21/31144 (2013.01);
Abstract

A method for mitigating line-edge roughness on a semiconductor device. The method includes line-edge roughness mitigation techniques in accordance with embodiments of the present invention. The techniques include: reducing the SiON film thickness below a conventional thickness; increasing the photoresist thickness above a conventional thickness; etching the SiON film with an etch bias power less than a conventional wattage amount with an overetch percentage less than a conventional overetch percentage; removing the SiON film layer immediately after completion of the amorphous carbon film layer etching; and lowering the lower electrode temperature below a conventional temperature.


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