The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Jun. 17, 2013
Applicant:

Analog Devices, Inc., Norwood, MA (US);

Inventors:

Eric Sagen, Longmont, CO (US);

Jonathan Kraft, Frederick, CO (US);

Kenneth G. Richardson, Erie, CO (US);

Assignee:

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05B 37/00 (2006.01); H05B 39/00 (2006.01); H05B 41/00 (2006.01); H05B 33/08 (2006.01);
U.S. Cl.
CPC ...
H05B 33/083 (2013.01); H05B 33/0815 (2013.01); H05B 33/0827 (2013.01); Y02B 20/347 (2013.01);
Abstract

A drive system for multiple LED strings powered by a common line voltage. Current control circuits are connected in series with respective LED strings; each current control circuit includes a drive transistor (typically a FET) which causes a desired LED string current to be conducted. In one embodiment, the current conducted by a selected one of the LED strings is controlled by the line voltage regulation loop, while the currents conducted by the remaining LED strings are controlled by respective local current loops, thus avoiding conflicts between the local current and line voltage regulation loops. The LED string to be current regulated by the line voltage regulation loop can be determined by a variety of criteria, such as the current control circuit having the maximum FET gate voltage, the minimum FET source voltage, the minimum FET drain voltage, the maximum FET gate-source voltage, or the minimum FET drain-source voltage.


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