The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Apr. 08, 2015
Applicants:

Hideki Sugimoto, Kanagawa, JP;

Akihiro Matsuoka, Kanagawa, JP;

Shimpei Sonoda, Kanagawa, JP;

Inventors:

Hideki Sugimoto, Kanagawa, JP;

Akihiro Matsuoka, Kanagawa, JP;

Shimpei Sonoda, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 1/00 (2006.01); G06K 1/00 (2006.01); G06K 15/00 (2006.01); H04N 1/32 (2006.01); G06T 1/20 (2006.01);
U.S. Cl.
CPC ...
H04N 1/32561 (2013.01); G06T 1/20 (2013.01);
Abstract

An accelerator circuit for an image processing apparatus includes a buffer circuit that temporarily stores image data obtained from N (N>1) data sources and an arithmetic circuit that performs a predetermined arithmetic operation on pixel data. The buffer circuit includes N buffer memories and N 2D registers associated with the respective N data sources, a control circuit, and a selector. Each buffer memory temporarily stores image data obtained from a corresponding one of the N data sources. Each 2D register temporarily stores pixel data, which is a part of image data stored in a corresponding one of the N buffer memories, of an area of a predetermined size. The selector is controlled by the control circuit so as to select, when pixel data is stored in one of the N 2D registers, the pixel data and send the pixel data to the arithmetic circuit.


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