The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Jul. 29, 2015
Applicant:

Honeywell International Inc., Morristown, NJ (US);

Inventors:

Balakrishna G. Gudi, Karnataka, IN;

Dinesh Kumar Kn, Karnataka, IN;

Aravind Sathyanarayana, Karnataka, IN;

Sandeep Pai, Karnataka, IN;

Assignee:

Honeywell International Inc., Morristown, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 27/14 (2006.01); H04B 1/10 (2006.01);
U.S. Cl.
CPC ...
H04L 27/14 (2013.01); H04B 1/10 (2013.01);
Abstract

A method of FSK decoding includes generating a pulse waveform (R'Edge) from a received FSK encoded signal (FSK signal) and a system clock (Sys_clk). From R'Edge and Sys_clk clocks are generated including a first clock and second clock framing a logic '0' level of the FSK signal, and a third clock and fourth clock framing a logic '1' level of the FSK signal. At least four frequency envelopes are generated from the clocks including a logic ‘0’ envelope, a logic ‘1’ envelope, a lower frequency envelope below the logic ‘0’ envelope, and an upper frequency envelope above the logic ‘1’ envelope. R'Edge is compared to the four envelopes, and a decoded output is produced, logic ‘0’ if the R'Edge overlaps the logic ‘0’ envelope, logic ‘1’ if R'Edge overlaps the logic ‘1’ envelope, and a previous output state if R'Edge does not overlap the logic ‘0’ or logic ‘1’ envelope.


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