The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Jan. 01, 2014
Applicant:

Phison Electronics Corp., Miaoli, TW;

Inventor:

Chien-Fu Tseng, Yunlin County, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); H03M 13/11 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1105 (2013.01); G06F 11/1012 (2013.01); H03M 13/1108 (2013.01); H03M 13/1111 (2013.01); H03M 13/1117 (2013.01);
Abstract

A decoding method, a memory storage device, a memory controlling circuit unit and a decoding circuit for low density parity code (LDPC) are provided. The decoding method includes: reading a data bit of each memory cell; performing a parity check procedure on the data bits to generate a plurality of checks; in an iterative decoding of LDPC, obtaining a reliability message of each data bit according to the checks and deciding an index of an error bit from the data bits according to the reliability messages; determining whether the index of the error bit and the checks comply with a parity criteria; and if the index of the error bit and the checks comply with the parity criteria, stopping the iterative decoding and outputting the index of the error bit. Accordingly, a decoding latency is decreased.


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