The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Feb. 28, 2014
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, Guangdong, CN;

Inventors:

Jinxiu Liu, Shenzhen, CN;

Shubao Guo, Shenzhen, CN;

Ding Li, Shenzhen, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/04 (2006.01); G06F 13/42 (2006.01); H03K 21/02 (2006.01); G06F 1/14 (2006.01); H03L 1/00 (2006.01); G04G 3/04 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
H03K 21/02 (2013.01); G04G 3/04 (2013.01); G06F 1/14 (2013.01); H03L 1/00 (2013.01); G06F 1/32 (2013.01);
Abstract

The present invention provides a correction circuit. The correction circuit includes a frequency dividing circuit, a frequency dividing coefficient operation circuit, a built-in temperature collection circuit, and a power-on and power-off detection circuit. The built-in temperature collection circuit is configured to collect a temperature of the chip; the power-on and power-off detection circuit is configured to detect power-on and power-off of the chip; the frequency dividing coefficient operation circuit is configured to calculate, according to the temperature of the chip collected by the built-in temperature collection circuit when the power-on and power-off detection circuit detects that the chip is powered off, a frequency dividing coefficient, and output the frequency dividing coefficient to the frequency dividing circuit; and the frequency dividing circuit is configured to provide, according to the frequency dividing coefficient output by the frequency dividing coefficient operation circuit, a timing pulse for a real-time clock.


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